Direct wafer bonding is a technique that enables two substrates with perfectly flat surfaces to be directly adhered to one another without the use of adhesives (paste, glue, etc.). This type of bonding is a technological step commonly used in the production of SOI and SeOI structures.
There are three basic methods of producing SeOI or SOI structures by direct bonding: the Smart Cut™ method, Bonded Silicon On Insulator (BSOI) or Bonded and Etchback Silicon On Insulator (BESOI) methods, and the ELTRAN® method. A description of the procedures involved in each of these methods can be found in the publication “Silicon wafer bonding technology for VLSI and MEMS applications”, S. S. Lyer and A. J. Auberton-Hervé, IEE (2002) and they are also well known to skilled artisans.
The SOI substrates obtained by direct wafer bonding according to these different methods include a buried insulating layer. Consequently, in order to create an insulating layer of silicon oxide (SiO2) on the original silicon substrate or substrates, thermal treatment can be applied in order to achieve wet or dry thermal oxidation of the silicon in the substrate surface. Alternatively, common depositing techniques such as CVD (Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapour Deposition) and PCVD (Plasma Chemical Vapour Deposition) can also be used.
The thickness of the thermal or deposited oxide layers varies depending on the final structure required, in other words, depending on the thickness of the buried insulating layer sought. In order to produce UTBOX substrates, the buried insulating layer has a thickness under 50 nm, preferably between 5 nm and 25 nm.
However, the thinness of the insulating layer of the UTBOX substrates makes molecular bonding difficult and indirectly affects the quality of the final substrate. Based on a constant production method, an SOI substrate characterized by a so-called thick buried insulator (typically having a thickness of over 100 nm) statistically exhibits far fewer bonding defects, as revealed following low-level thermal treatment, than a substrate with a very thin buried insulator.
In fact, with UTBOX structures, the species present at bonding interface level, such as water, hydrogen, hydrocarbons or species resulting from an implantation stage, can no longer find sufficient trapping sites within the thin oxide layer and diffuse along the bonding interface where they coalesce, giving rise to numerous structural defects.
In the case of a thin layer transfer using Smart Cut™ technology, the main defects exacerbated on the final structures by the extreme thinness of the buried insulator are referred to as “blisters” and “non-transferred zones”. As is shown in FIG. 1, they lead to holes of different sizes in the active layer 10, but these are always “killer” defects for the device produced from these substrates.
The non-transferred zones 200, known by the abbreviation “NTZ” or else referred to as “voids”, are holes in the active layer 10 and the buried insulator 3 of a size typically between 0.1 μm and 3 mm. An NTZ 200 corresponds to a zone in an active layer 10 resulting from a donor substrate 1, also referred to as the first substrate, which is not transferred to the receiver substrate 2, also referred to as the second substrate. When these NTZs are localized on the periphery of the final structure, more precisely at a distance typically between 1 and 5 mm from the edge of the substrate, they are referred to as edge voids 300.
An edge void 300 is a hole with a diameter typically between 50 μm and 3 mm in the thin transferred layer 10.
A blister 400 corresponds to a zone of transferred film that is removed from the receiver substrate 2 under pressure from an accumulated gas bubble at the bonding interface. Since the film that is lifted locally is very fragile, a blister 400 invariably leads to a hole in the final structure, with a diameter typically between 0.5 and 3 mm.
All holes in the centre or on the edge of the wafer, whether microscopic or macroscopic in size, are killer defects, because in the absence of an active layer for the creation of electronic components, no component can be produced on this site. A greater number of NTZs 200, edge voids 300 and blisters 400 are therefore synonymous with a decline in quality and a drop in yield.
In order to reduce the number of defects associated with the bonding stage and reinforce the bonding interface, the substrates may undergo plasma activation before they are brought into contact. “Plasma activation” of a bonding surface is defined as the exposure of this surface to plasma (which, notably, may take place in a vacuum or at atmospheric pressure).
More precisely, in the known activation techniques, the surface of a section to be activated is exposed to plasma at an exposure stage in which the exposure parameters are controlled, so that each one is set at a given value that remains fixed throughout the plasma activation.
The principle “exposure parameters” are:    power density. This is the power density supplied to the plasma, which translates a power density by unit area (W/cm2) and will likewise be referred to in this text simply using the term “power”.    pressure (pressure in the vessel holding the plasma),    the nature and output of the gas supplying this vessel, and    the activation duration.
Activation of this type makes it possible, in particular, to execute direct wafer bonding by achieving significant bonding energies without having to resort to thermal treatment which must, necessarily, be carried out at high temperatures.
In effect, plasma activation makes it possible to obtain high bonding energies between two substrates, at least one of which has been activated prior to bonding, following thermal treatment carried out for relatively short durations (around 2 hours, for example) and at relatively low temperatures (around 600° C. or less, for example).
Activation of this type is therefore advantageous in stabilizing a structure comprising two bonded substrates, if the intention is to avoid subjecting the structure to excessively high temperatures (particularly in the case of heterostructures, which are defined as structures made up of layers of materials with significantly different thermal expansion coefficients).
Activation of this type may also be advantageous in achieving significant bonding strengths at a given temperature.
Activation of this type is therefore advantageous, for example, in achieving multilayer structures involving the bonding of two substrates.
The transfer procedures (particularly Smart Cut™ procedures for which a general description is given in the publication SILICON-ON-INSULATOR TECHNOLOGY: Materials to VLSI, 2nd Edition (Jean-Pierre COLINGE), or BESOI (Bond Etch Silicon On Insulator) procedures, in which two substrates are bonded then the surplus material is removed from one of the substrates by etching, or the ELTRAN™ procedure) are examples of applications that can benefit from plasma activation to support bonding.
In order to benefit fully from the effects of plasma treatment for each bonding, the standard procedure found in the literature (notably in the documents entitled Effects of plasma activation on hydrophilic bonding of Si and SiO2, T. Suni and l. J. Electroch. Soc. Vol. 149, no 6, p. 348 (2002) and in the U.S. Pat. No. 6,180,496 by Farrens et al.) involves the plasma activation of one or both bonding substrates.
Different gases are used today in plasma treatments, in order to activate the wafer surfaces before they are brought into contact, including, for instance, oxygen, nitrogen and argon. However, although the various techniques currently used favour a high bonding energy at the interfaces, they do not allow very high quality semiconductor structures to be produced with thin or even ultra-thin insulating layers. Thus, improvements in these techniques are needed.